eVS has developed IP² core lib, a collection of basic and advanced functional blocks for image processing in FPGA.
Basic blocks include noise reduction, mophological filters, histogram stretching, edge detection, image segmentation, etc.
Advanced blocks are instead about image warping, stereo matching and object detection.
IP² core lib is optimized for Xilinx FPGAs, in particular the Xilinx Zynq®7000 All Programmable SoCs, combining programmable logic and high-performance embedded processor on the same chip, provide the most effective solution for targeting DA algorithms demanding both intensive pixel-level calculus and high level complex control. IP cores are well tested, ready to use, and can be simply configured and combined to each other to build complex design.
eVS is member of the Xilinx Alliance Program.
